1. Field of the Invention
The present invention generally relates to digital-to-analog converters (DACs), and more specifically to a DAC that generates an approximately piecewise linear analog waveform with reduced spectral distortion and increased signal-to-quantization-noise ratio (SQNR).
2. Description of the Related Art
DACs are used to convert a sequence of digital codewords, where each codeword represents a quantized sample from an underlying analog waveform, into an analog voltage or current signal. In digital circuits each bit of the codeword is represented by a digital signal. In theory, these signals could be binary weighted, as a function of the bit's position, and summed together to produce the analog signal. However, the digital signals are only controlled with sufficient accuracy to switch the digital circuitry, and thus are not precise enough to accurately construct the analog signal. Instead, the digital signals are used to control electrical switches that switch between precision limited low and high signal levels. These signals are binary weighted and summed together to give the analog signal. As the speed of digital circuitry increases, the slew rate (switching speed) and accuracy of the switches become increasingly important factors in minimizing distortion of the analog signal.
FIG. 1 is a schematic diagram of a conventional DAC 10 that converts a sequence of n-bit binary codewords 12 into an analog voltage signal V.sub.0. A clock 14 applies a clock signal 16 to a register 18 so that each codeword is read out in parallel. Register 18 produces n digital signals 20, one for each bit of codeword 12, that are applied to respective digitally controlled electrical switches S.sub.N-1, S.sub.N-2, . . . , S.sub.0 and held for a complete clock cycle. The codewords' most significant bits (MSBs) are applied to switch S.sub.N-1 and their least significant bits (LSBs) are applied to switch S.sub.O.
A reference voltage line -V.sub.R and a ground line GND are selectively applied through digitally controlled electrical switches S.sub.N-1, S.sub.N-2, . . . , S.sub.0 to respective binary weighted resistors R.sub.N-1, R.sub.N-2, . . . , R.sub.0. The resistors are connected in parallel to the inverting terminal 22 of an inverting operational amplifier (opamp) A1. The opamp's non-inverting terminal 24 is connected to ground, and a resistor R.sub.out is connected between inverting terminal 22 and opamp output 26. The negative feedback of opamp A1 holds the voltage at inverting terminal 22 at approximately ground potential.
When the MSB of codeword 12 is high, switch S.sub.N-1, connects the reference voltage line -V.sub.R to resistor R.sub.N-1, which causes a current I.sub.N-1 to flow through it. Because the resistor values are binary weighted, i.e. R.sub.N-1 =R, R.sub.N-2 =2R, . . . , and R.sub.0 =2.sup.N-1 R, the currents are related as I.sub.N-1 =2I.sub.N-2 =. . . 2.sup.N-1 I.sub.0 so that they reflect the significance of their associated bits. When the MSB is low, switch S.sub.N-1 connects the ground line to resistor R.sub.N-1 so that the voltage drop across resistor R.sub.N-1 is ideally zero, and hence the current I.sub.N-1 is zero. The currents I.sub.N-1, . . . , I.sub.0 are summed at inverting terminal 22 to produce a current I.sub.sum that is proportional to codeword 12. I.sub.sum flows through R.sub.out and generates voltage V.sub.0 at output 26.
Voltage signal V.sub.0 is given by: ##EQU1## where a.sub.N-1, . . . , a.sub.0 are the binary coefficients for the MSB to the LSB and R is the resistance of R.sub.N-1.
Factoring equation 1 gives: ##EQU2## which shows that V.sub.0 is proportional to the digital codeword 12.
As shown in FIG. 2, the ideal voltage signal V.sub.0 is a zero-order-hold (ZOH) or stair-stepped waveform 28 with infinite slew rate (a discontinuity at the sampling instances) that represents the quantized samples 29 of an underlying analog waveform 30. The DAC's output voltage signal V.sub.0 is filtered to produce a reconstructed analog waveform 32 that is a time-shifted approximation of the underlying waveform 30. For DAC 10 to produce an ideal ZOH waveform 28, the switches S.sub.N-1, . . . S.sub.0 have to switch and settle between the desired plateau levels instantaneously. However, in practice switches can not switch instantly, and will overshoot and ring before settling to the plateau levels. Under conventional theory, the accuracy of DAC 10 depends upon how close the switches' actual transfer functions approximate ideal ZOH waveform 28.
As shown in FIG. 3, each switch S.sub.N-1, . . . , and S.sub.0 produces an output waveform 34 that follows a rising edge 36 at a finite slew rate, i.e. a non-zero rise time T.sub.R1, overshoots the desired plateau level 38, and rings for a portion of the clock period T before settling to plateau level 38. The rise time T.sub.R1 is defined as the time it takes for waveform 34 to rise from 10% to 90% of the difference between the high and low plateau levels. The slew rate is the ten-to-ninety percent change in the amplitude divided by rise time T.sub.R1. Settling time T.sub.S1 is the time it takes for waveform 34 to rise from the 10% level and settle to within a known error bound 40, suitably one-half of an LSB, from desired plateau level 38. In practice, each switch is designed to approximate an ideal ZOH waveform 42 by minimizing the settling time T.sub.S1.
A well known approach for reducing settling time T.sub.S1 is to reduce the switch's rise time T.sub.R1. The switch's ringing is dampened by reducing its parasitic capacitance and inductance. However, manufacturing a switch with these characteristics is difficult and expensive. Furthermore, even though the switch's waveform 34 approximates the ZOH waveform 42 it would be preferable to reduce its spectral distortion even further.
Kamoto et al. "An 8-bit 2-ns Monolithic DAC," IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, Feb. 1988, pp. 142-146 disclose a DAC that reduces the settling time T.sub.S2 of its output waveform 44 (shown in FIG. 3) by controlling the switches' rise and fall times. For each codeword bit, a differential digital signal is applied through a control driver to a switch that is driven between precision limited low and high values. The control driver increases the digital signal's rise time, which has the effect of increasing the switch's rise time T.sub.R2. This suppresses the ringing and reduces the settling time T.sub.S2.
The control driver is adjusted externally to select the optimum rise time that minimizes settling time T.sub.S2. Kamoto shows that when rise time T.sub.R2 is too short, ringing is severe and settling time T.sub.S2 is increased. However, if rise time T.sub.R2 is too long settling time T.sub.S2 will also be increased, and hence degrade waveform 44. At the optimum rise time, the countervailing interests of reducing the rise time and suppressing the ringing are balanced and thus provide the minimum settling time. Kamoto discloses optimum rise and fall times of approximately fifteen percent of the settling time.
Because Kamoto is trying to approximate ZOH waveform 42 the rise time, and hence slew rate, must remain relatively fast to construct the rising edge of the ZOH waveform. At these relatively large slew rates, high frequency parasitic effects cause the waveform's rising edge 46 to be non-linear. Furthermore, waveform 44 still overshoots the desired plateau value 38 and rings for a period of time. The non-linearity of rising edge 46 and the ringing in waveform 44 cause spectral distortion that would preferably be reduced.